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March 2004
(R)
AS7C31025B
3.3V 128K X 8 CMOS SRAM (Center power and ground) Features
* Industrial and commercial temperatures * Organization: 131,072 x 8 bits * High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE - 252 mW / max @ 10 ns * Low power consumption: STANDBY - 18 mW / max CMOS * 6 T 0.18 u CMOS technology * * * * Easy memory expansion with CE, OE inputs Center power and ground TTL/LVTTL-compatible, three-state I/O JEDEC-standard packages - 32-pin, 300 mil SOJ - 32-pin, 400 mil SOJ * ESD protection 2000 volts * Latch-up current 200 mA
Pin arrangement Logic block diagram
VCC GND Input buffer A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O7 32-pin SOJ (300 mil) 32-pin SOJ (400 mil)
A0 A1 A2 A3 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A12 A11 A10 A9 A8
Row decoder
512 x 256 x 8 Array (1,048,576)
I/O0 WE OE CE
Column decoder A9 A10 A11 A12 A13 A14 A15 A16
Control circuit
Selection guide
-10 Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current 10 5 70 5 -12 12 6 65 5 -15 15 7 60 5 -20 20 8 55 5 Unit ns ns mA mA
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Alliance Semiconductor
AS7C31025B
Sense amp
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Functional description
The AS7C31025B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications. The chip enable input CE permits easy memory and expansion with multiple-bank memory systems. When CE is high the device enters standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are TTL-compatible, and operation is from a single 3.3 V supply. The AS7C31025B is packaged in common industry standard packages.
Absolute maximum ratings
Parameter Voltage on VCC relative to GND Voltage on any pin relative to GND Power dissipation Storage temperature (plastic) Ambient temperature with VCC applied DC current into outputs (low) Symbol Vt1 Vt2 PD Tstg Tbias IOUT Min -0.50 -0.50 - -65 -55 - Max +5.0 VCC + 0.5 1.0 +150 +125 20 Unit V V W
o
C
oC
mA
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CE H L L L WE X H H L OE X H L X Data High Z High Z DOUT DIN Mode Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
Key: X = don't care, L = low, H = high.
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Recommended operating conditions
Parameter Supply voltage Input voltage Ambient operating temperature
VIL = -1.0V for pulse width less than 5ns
VIH = VCC + 1.5V for pulse width less than 5ns
Symbol VCC VIH VIL TA TA
Min 3.0 2.0 -0.5 0 -40
Nominal 3.3 - - - -
Max 3.6 VCC + 0.5 0.8 70 85
Unit V V V
o
C
oC
DC operating characteristics (over the operating range)1
-10 Parameter
Input leakage current Output leakage current Operating power supply current
-12
-15
-20
Sym
| ILI | | ILO |
Test conditions VCC = Max, VIN = GND to VCC VCC = Max, CE = VIH, Vout = GND to VCC VCC = Max CE VIL, f = fMax, IOUT = 0 mA VCC = Max CE VIH, f = fMax VCC = Max, CE VCC-0.2 V, VIN 0.2 V or VIN VCC -0.2 V, f=0 IOL = 8 mA, VCC = Min IOH = -4 mA, VCC = Min
Min Max Min Max Min Max Min Max Unit
- - 1 1 - - 1 1 - - 1 1 - - 1 1 A A
ICC
-
70
-
65
-
60
-
55
mA
ISB Standby power supply current1 ISB1 VOL VOH
-
30
-
25
-
20
-
20
mA
- - 2.4
5
0.4 -
- - 2.4
5
0.4 -
- - 2.4
5
0.4 -
- - 2.4
5
0.4 -
mA V V
Output voltage
Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CE, WE, OE I/O Test conditions VIN = 0 V VIN = VOUT = 0 V Max 5 7 Unit pF pF
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Read cycle (over the operating range)3,9
-10 Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change CE low to output in low Z CE high to output in high Z OE low to output in low Z OE high to output in high Z Power up time Power down time Symbol tRC tAA tACE tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD Min 10 - - - 3 3 - 0 - 0 - Max - 10 10 5 - - 3 - 5 - 10 12 - - - 3 3 - 0 - 0 - -12 Min Max - 12 12 6 - - 3 - 6 - 12 15 - - - 3 3 - 0 - 0 - -15 Min Max - 15 15 7 - - 4 - 7 - 15 20 - - - 3 3 - 0 - 0 - -20 Min Max - 20 20 8 - - 5 - 8 - 20 Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 3 3 Notes
Key to switching waveforms
Rising input Falling input Undefined/don't care
Read waveform 1 (address controlled)3,6,7,9
tRC Address DOUT tAA Data valid tOH
Read waveform 2 (CE and OE controlled)3,6,8,9
CE tOE OE DOUT Supply current tACE tCLZ tPU Data valid tPD 50% 50% ICC ISB tOLZ tOHZ tCHZ tRC1
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Write cycle (over the operating range)11
-10 Parameter Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Write recovery time Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW tAW tAS tWP tWR tAH tDW tDH tWZ tOW 10 8 8 0 7 0 0 5 0 - 1 - - - - - - - - - 5 - 12 9 9 0 8 0 0 6 0 - 1 -12 - - - - - - - - - 6 - 15 10 10 0 9 0 0 8 0 - 1 -15 - - - - - - - - - 7 - 20 12 12 0 12 0 0 10 0 - 1 -20 Unit ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 Notes - - - - - - - - - 8 - Min Max Min Max Min Max Min Max
Write waveform 1 (WE controlled)10,11
tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tWR tAH
Write waveform 2 (CE controlled)10,11
tAW Address tAS CE WE tWZ DIN DOUT tWP tDW Data valid tDH tCW tWC tAH tWR
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AC test conditions
- - - - Output load: see Figure B. Input pulse level: GND to 3.0 V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5 V.
Thevenin equivalent: 168 DOUT +1.728 V +3.3 V 320 +3.0 V GND 90% 10% 2 ns 90% 10% DOUT 255 C13
Figure A: Input pulse
GND Figure B: 3.3 V Output load
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions, Figures A and B. tCLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE and OE are low for read cycle. Address is valid prior to or coincident with CE transition low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
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Package dimensions
32-pin SOJ 300 mil/400 mil e D
E1 E2
Pin 1 A1 c A2 E
B A b Seating plane
32-pin SOJ 300 mil Symbol A A1 A2 B b c D E E1 E2 e Min 0.128 0.025 0.095 0.026 0.016 0.007 0.820 0.255 0.295 0.330 Max 0.145 0.105 0.032 0.020 0.010 0.830 0.275 0.305 0.340
32-pin SOJ 400 mil Min 0.132 0.025 0.105 0.026 0.015 0.007 0.820 0.354 0.395 0.435 Max 0.146 0.115 0.032 0.020 0.013 0.830 0.378 0.405 0.445
0.050 BSC
0.050 BSC
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Ordering Codes
Package \ Access time 300-mil SOJ 400-mil SOJ Temperature
Commercial Industrial Commercial Industrial
10 ns
AS7C31025B-10TJC AS7C31025B-10TJI AS7C31025B-10JC AS7C31025B-10JI
12 ns
AS7C31025B-12TJC AS7C31025B-12TJI AS7C31025B-12JC AS7C31025B-12JI
15 ns
AS7C31025B-15TJC AS7C31025B-15TJI AS7C31025B-15JC AS7C31025B-15JI
20 ns
AS7C31025B-20TJC AS7C31025B-20TJI AS7C31025B-20JC AS7C31025B-0JI
Note: Add suffix `N' to the above part number for lead free parts (Ex. AS7C31025B-10TJCN)
Part numbering system
AS7C SRAM prefix X Voltage: 3 = 3.3 V CMOS 1025B Device number -XX Access time X X X N=Lead Free Part Package: Temperature range TJ = SOJ 300 mil C = commercial, 0 C to 70 C J = SOJ 400 mil I = industrial, -40 C to 85 C
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AS7C31025B
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Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel: 408 - 855 - 4900 Fax: 408 - 855 - 4999 www.alsc.com
Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: AS7C31025B Document Version: v. 1.3
(c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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